Intel® Quartus® Prime Standard Edition User Guide: Platform Designer

ID 683364
Date 12/15/2018
Public
Document Table of Contents

4.1.6.1. AXI Bridge Signal Types

Based on parameter selections that you make for the AXI Bridge component, Platform Designer instantiates either the AMBA* 3 AXI or AMBA* 3 AXI master and slave interfaces into the component.

Note: In AMBA* 3 AXI, aw/aruser accommodates sideband signal usage by hard processor systems (HPS).
Table 86.  Sets of Signals for the AXI Bridge Based on the Protocol
Signal Name AMBA* 3 AXI AMBA* 3 AXI
awid / arid yes yes
awaddr / araddr yes yes
awlen / arlen yes (4-bit) yes (8-bit)
awsize / arsize yes yes
awburst / arburst yes yes
awlock / arlock yes yes (1-bit optional)
awcache / arcache yes (2-bit) yes (optional)
awprot / arprot yes yes
awuser / aruser yes yes
awvalid / arvalid yes yes
awready / arready yes yes
awqos / arqos no yes
awregion / arregion no yes
wid yes no (optional)
wdata / rdata yes yes
wstrb yes yes
wlast / rvalid yes yes
wvalid / rlast yes yes
wready / rready yes yes
wuser / ruser no yes
bid / rid yes yes
bresp / rresp yes yes (optional)
bvalid yes yes
bready yes yes