Intel® Quartus® Prime Standard Edition User Guide: Platform Designer

ID 683364
Date 12/15/2018
Public
Document Table of Contents

3.5.4.3.2. Reset Sequencer Interrupt Enable Register

The Interrupt Enable register bits enable events triggering the IRQ of the reset sequencer.
Table 59.  Values for the Interrupt Enable Register at Offset 0x04
Bit Attribute Default Description
31 Reserved.
30 RW 0 Interrupt on Reset Asserted and waiting for SW to proceed enable. When set, the IRQ is set when the sequencer is waiting for the software to proceed in an assertion sequence.
29 RW 0 Interrupt on Reset Deasserted and waiting for SW to proceed enable. When set, the IRQ is set when the sequencer is waiting for the software to proceed in a deassertion sequence.
28:26 Reserved.
25:16 RW 0 Interrupt on Reset deassertion input qualification signal reset_dsrt_qual_[9:0] status— When set, the IRQ is set when the reset_dsrt_qual[9:0] status bit (per bit enable) is set.
15:12 Reserved.
11 RW 0 Interrupt on reset_in9 Enable—When set, the IRQ is set when the reset_in9 trigger status bit is set.
10 RW 0 Interrupt on reset_in8 Enable—When set, the IRQ is set when the reset_in8 trigger status bit is set.
9 RW 0 Interrupt on reset_in7 Enable—When set, the IRQ is set when the reset_in7 trigger status bit is set.
8 RW 0 Interrupt on reset_in6 Enable—When set, the IRQ is set when the reset_in6 trigger status bit is set.
7 RW 0 Interrupt on reset_in5 Enable—When set, the IRQ is set when the reset_in5 trigger status bit is set.
6 RW 0 Interrupt on reset_in4 Enable—When set, the IRQ is set when the reset_in4 trigger status bit is set.
5 RW 0 Interrupt on reset_in3 Enable—When set, the IRQ is set when the reset_in3 trigger status bit is set.
4 RW 0 Interrupt on reset_in2 Enable—When set, the IRQ is set when the reset_in2 trigger status bit is set.
3 RW 0 Interrupt on reset_in1 Enable—When set, the IRQ is set when the reset_in1 trigger status bit is set.
2 RW 0 Interrupt on reset_in0 Enable—When set, the IRQ is set when the reset_in0 trigger status bit is set.
1 RW 0 Interrupt on Software triggered reset Enable—When set, the IRQ is set when the software triggered reset status bit is set.
0 RW 0 Interrupt on Power-On-Reset Enable—When set, the IRQ is set when the power-on-reset status bit is set.