Intel® Quartus® Prime Standard Edition User Guide: Platform Designer

ID 683364
Date 12/15/2018
Public
Document Table of Contents

4.9. Avalon® -ST Streaming Pipeline Stage

The Avalon® -ST pipeline stage receives data from an Avalon® -ST source interface, and outputs the data to an Avalon® -ST sink interface. In the absence of back pressure, the Avalon® -ST pipeline stage source interface outputs data one cycle after receiving the data on its sink interface.

If the pipeline stage receives back pressure on its source interface, it continues to assert its source interface's current data output. While the pipeline stage is receiving back pressure on its source interface and it receives new data on its sink interface, the pipeline stage internally buffers the new data. It then asserts back pressure on its sink interface.

After the backpressure is deasserted, the pipeline stage's source interface is deasserted and the pipeline stage asserts internally buffered data (if present). Additionally, the pipeline stage deasserts back pressure on its sink interface.

Figure 141.  Pipeline Stage Simple Register If the ready signal is not pipelined, the pipeline stage becomes a simple register.
Figure 142. Pipeline Stage Holding Register If the ready signal is pipelined, the pipeline stage must also include a second "holding" register.