Intel® Quartus® Prime Standard Edition User Guide: Platform Designer

ID 683364
Date 12/15/2018
Public
Document Table of Contents

4.8.2.2. Packets to Transactions Converter Supported Transactions

The Packets to Transactions Converter core supports the following Avalon® -MM transactions:

Table 154.  Packets to Transactions Converter Supported Transactions
Transaction Code Avalon® -MM Transaction Description
0x00 Write, non-incrementing address. Writes data to the address until the total number of bytes written to the same word address equals to the value specified in the size field.
0x04 Write, incrementing address. Writes transaction data starting at the current address.
0x10 Read, non-incrementing address. Reads 32 bits of data from the address until the total number of bytes read from the same address equals to the value specified in the size field.
0x14 Read, incrementing address. Reads the number of bytes specified in the size parameter starting from the current address.
0x7f No transaction. No transaction is initiated. You can use this transaction type for testing purposes. Although no transaction is initiated on the Avalon® -MM interface, the core still returns a response packet for this transaction code.

The Packets to Transactions Converter core can process only a single transaction at a time. The ready signal on the core's Avalon® -ST sink interface is asserted only when the current transaction is completely processed.

No internal buffer is implemented on the datapaths. Data received on the Avalon® -ST interface is forwarded directly to the Avalon® -MM interface and vice-versa. Asserting the waitrequest signal on the Avalon® -MM interface backpressures the Avalon® -ST sink interface. In the opposite direction, if the Avalon® -ST source interface is backpressured, the read signal on the Avalon® -MM interface is not asserted until the backpressure is alleviated. Backpressuring the Avalon® -ST source in the middle of a read can result in data loss. In this cases, the core returns the data that is successfully received.

A transaction is considered complete when the core receives an EOP. For write transactions, the actual data size is expected to be the same as the value of the size property. Whether or not both values agree, the core always uses the end of packet (EOP) to determine the end of data.