Intel® Quartus® Prime Standard Edition User Guide: Platform Designer
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Ixiasoft
Visible to Intel only — GUID: mwh1409958777068
Ixiasoft
5. Creating Platform Designer Components
Refer to the Demo AXI Memory example on the Design Examples page for full code examples that appear in this chapter.
Platform Designer supports Avalon® , AMBA* 3 AXI (version 1.0), AMBA* 4 AXI (version 2.0), AMBA* 4 AXI-Lite (version 2.0), AMBA* 4 AXI-Stream (version 1.0), and AMBA* 3 APB (version 1.0) interface specifications.
Section Content
Platform Designer Components
Design Phases of an IP Component
Create IP Components in the Platform Designer Component Editor
Specify IP Component Type Information
Create an HDL File in the Platform Designer Component Editor
Create an HDL File Using a Template in the Platform Designer Component Editor
Specify Synthesis and Simulation Files in the Platform Designer Component Editor
Add Signals and Interfaces in the Platform Designer Component Editor
Specify Parameters in the Platform Designer Component Editor
Declaring SystemVerilog Interfaces in _hw.tcl
User Alterable HDL Parameters in _hw.tcl
Scripting Wire-Level Expressions
Control Interfaces Dynamically with an Elaboration Callback
Control File Generation Dynamically with Parameters and a Fileset Callback
Create a Composed Component or Subsystem
Create an IP Component with Platform Designer a System View Different from the Generated Synthesis Output Files
Add Component Instances to a Static or Generated Component
Creating Platform Designer Components Revision History