Intel® Quartus® Prime Standard Edition User Guide: Platform Designer

ID 683364
Date 12/15/2018
Public
Document Table of Contents

3.9.7. Data Buses

Narrow bus transfers are supported. AXI write strobes can have any pattern that is compatible with the address and size information. Intel recommends that transactions to Avalon® slaves follow Avalon® byteenable limitations for maximum compatibility.
Note: Byte 0 is always bits [7:0] in the interconnect, following AXI's and Avalon® 's byte (address) invariance scheme.