Intel® Quartus® Prime Standard Edition User Guide: Platform Designer

ID 683364
Date 12/15/2018
Public
Document Table of Contents

1.14. Simulating a Platform Designer System

You can simulate a Platform Designer system in a supported third-party simulator to verify and debug operation. Platform Designer generates the simulation models for your system, along with optional scripts to set up the simulation environment for specific, supported third-party simulators.

You can use scripts to compile the required device libraries and system design files in the correct order and elaborate or load the top-level system for simulation.

Table 19.  Simulation Script VariablesThe simulation scripts provide variables that allow flexibility in your simulation environment.
Variable Description
TOP_LEVEL_NAME If the testbench Platform Designer system is not the top‑level instance in your simulation environment because you instantiate the Platform Designer testbench within your own top-level simulation file, set the TOP_LEVEL_NAME variable to the top-level hierarchy name.
QSYS_SIMDIR If the simulation files generated by Platform Designer are not in the simulation working directory, use the QSYS_SIMDIR variable to specify the directory location of the Platform Designer simulation files.
QUARTUS_INSTALL_DIR Points to the Quartus installation directory that contains the device family library.

Top-Level Simulation HDL File for a Testbench System

The example below shows the pattern_generator_tb generated for a Platform Designer system called pattern_generator. The top.sv file defines the top-level module that instantiates the pattern_generator_tb simulation model, as well as a custom SystemVerilog test program with BFM transactions, called test_program.

module top();
 pattern_generator_tb tb();
 test_program pgm();
endmodule
Note: The VHDL version of the Tristate Conduit BFM component is not supported in Synopsys VCS, NCSim, and Riviera-PRO in the Intel® Quartus® Prime software version 14.0. These simulators do not support the VHDL protected type, which is used to implement the BFM. For a workaround, use a simulator that supports the VHDL protected type.