Intel® Quartus® Prime Standard Edition User Guide: Platform Designer

ID 683364
Date 12/15/2018
Public
Document Table of Contents

3.5.4.4.2. Reset Assert Flow

The following flow sequence occurs for a Reset Assert Flow:

  • A reset is triggered either by the software, or when input resets to the Reset Sequencer are asserted.
  • The IRQ is asserted, if the IRQ is enabled.
  • Software reads the Status register to determine which reset was triggered.