Intel® Quartus® Prime Standard Edition User Guide: Platform Designer

ID 683364
Date 12/15/2018
Public
Document Table of Contents

7.2.13. Module Properties

Name Description
ANALYZE_HDL When set to false, prevents a call to the Intel® Quartus® Prime mapper to verify port widths and directions, speeding up generation time at the expense of fewer validation checks. If this property is set to false, invalid port widths and directions are discovered during the Intel® Quartus® Prime software compilation. This does not affect IP components using filesets to manage synthesis files.
AUTHOR The IP component author.
COMPOSITION_CALLBACK The name of the composition callback. If you define a composition callback, you cannot not define the generation or elaboration callbacks.
DATASHEET_URL Deprecated. Use add_documentation_link to provide documentation links.
DESCRIPTION The description of the IP component, such as "This IP component implements a half-rate bridge."
DISPLAY_NAME The name to display when referencing the IP component, such as "My Platform Designer IP Component".
EDITABLE Indicates whether you can edit the IP component in the Component Editor.
ELABORATION_CALLBACK The name of the elaboration callback. When set, the IP component's elaboration callback is called to validate and elaborate interfaces for instances of the IP component.
GENERATION_CALLBACK The name for a custom generation callback.
GROUP The group in the IP Catalog that includes this IP component.
ICON_PATH A path to an icon to display in the IP component's parameter editor.
INSTANTIATE_IN_SYSTEM_MODULE If true, this IP component is implemented by HDL provided by the IP component. If false, the IP component creates exported interfaces allowing the implementation to be connected in the parent.
INTERNAL An IP component which is marked as internal does not appear in the IP Catalog. This feature allows you to hide the sub-IP-components of a larger composed IP component.
MODULE_DIRECTORY The directory in which the hw.tcl file exists.
MODULE_TCL_FILE The path to the hw.tcl file.
NAME The name of the IP component, such as my_qsys_component.
OPAQUE_ADDRESS_MAP For composed IP components created using a _hw.tcl file that include children that are memory-mapped slaves, specifies whether the children's addresses are visible to downstream software tools. When true, the children's address are not visible. When false, the children's addresses are visible.
PREFERRED_SIMULATION_LANGUAGE The preferred language to use for selecting the fileset for simulation model generation.
REPORT_HIERARCHY null
STATIC_TOP_LEVEL_MODULE_NAME Deprecated.
STRUCTURAL_COMPOSITION_CALLBACK The name of the structural composition callback. This callback is used to represent the structural hierarchical model of the IP component and the RTL can be generated either with module property COMPOSITION_CALLBACK or by ADD_FILESET with target QUARTUS_SYNTH
SUPPORTED_DEVICE_FAMILIES A list of device family supported by this IP component.
TOP_LEVEL_HDL_FILE Deprecated.
TOP_LEVEL_HDL_MODULE Deprecated.
UPGRADEABLE_FROM null
VALIDATION_CALLBACK The name of the validation callback procedure.
VERSION The IP component's version, such as 10.0.