Intel® Quartus® Prime Standard Edition User Guide: Platform Designer

ID 683364
Date 12/15/2018
Public
Document Table of Contents

4.4.3.3.3. Test Pattern Checker Control and Status Registers

Table 106.  Test Pattern Checker Control and Status Register MapShows the offset for the control and status registers. Each register is 32 bits wide.

Offset

Register Name

base + 0

status

base + 1

control

base + 2

Reserved

base + 3

base + 4

base + 5

exception_descriptor

base + 6

indirect_select

base + 7

indirect_count
Table 107.  Test Pattern Checker Status Register Bits

Bit(s)

Name

Access

Description

[15:0]

ID

RO

Contains a constant value of 0x65.

[23:16]

NUMCHANNELS

RO

The configured number of channels.

[30:24]

NUMSYMBOLS

RO

The configured number of symbols per beat.

[31]

SUPPORTPACKETS

RO

A value of 1 indicates packet support.

Table 108.  Test Pattern Checker Control Register Bits

Bit(s)

Name

Access

Description

[0]

ENABLE

RW

Setting this bit to 1 enables the test pattern checker.

[7:1]

Reserved

[16:8]

THROTTLE

RW

Specifies the throttle value which can be between 0–256, inclusively. Platform Designer uses this value in conjunction with a pseudo-random number generator to throttle the data generation rate.

Setting THROTTLE to 0 stops the test pattern generator core. Setting it to 256 causes the test pattern generator core to run at full throttle. Values between 0–256 result in a data rate proportional to the throttle value.

[17]

SOFT RESET

RW

When this bit is set to 1, all internal counters and statistics are reset. Write 0 to this bit to exit reset.

[31:18]

Reserved

If there is no exception, reading the exception_descriptor register bit register returns 0.

Table 109.   exception_descriptor Register Bits

Bit(s)

Name

Access

Description

[0]

DATA ERROR

RO

A value of 1 indicates that an error is detected in the incoming data.

[1]

MISSINGSOP

RO

A value of 1 indicates missing start-of-packet.

[2]

MISSINGEOP

RO

A value of 1 indicates missing end-of-packet.

[7:3]

Reserved

[15:8]

SIGNALLED ERROR

RO

The value of the error signal.

[23:16]

Reserved

[31:24]

CHANNEL

RO

The channel on which the exception was detected.

Table 110.   indirect_select Register Bits

Bit

Bits Name

Access

Description

[7:0]

INDIRECT CHANNEL

RW

Specifies the channel number that applies to the INDIRECT PACKET COUNT, INDIRECT SYMBOL COUNT, and INDIRECT ERROR COUNT registers.

[15:8]

Reserved

[31:16]

INDIRECT ERROR

RO

The number of data errors that occurred on the channel specified by INDIRECT CHANNEL.

Table 111.   indirect_count Register Bits

Bit

Bits Name

Access

Description

[15:0]

INDIRECT PACKET COUNT

RO

The number of data packets received on the channel specified by INDIRECT CHANNEL.

[31:16]

INDIRECT SYMBOL COUNT

RO

The number of symbols received on the channel specified by INDIRECT CHANNEL.

.