Intel® Quartus® Prime Standard Edition User Guide: Platform Designer

ID 683364
Date 12/15/2018
Public
Document Table of Contents

3.7.1. Manually Control Pipelining in the Platform Designer Interconnect

The Memory-Mapped Interconnect tab allows you to manipulate pipeline connections in the Platform Designer interconnect.
Consider manually pipelining the interconnect only when changes to the Limit interconnect pipeline stages to option do not improve frequency, and exhausted all other options to achieve timing closure, including the use of a bridge. Perform manual pipelining only in complete systems.

Access the Memory-Mapped Interconnect tab by clicking System > Show System With Platform Designer Interconnect

  1. In the Intel® Quartus® Prime software, compile the design and run timing analysis.
  2. From the timing analysis output, identify the critical path through the interconnect and determine the approximate mid-point.
  3. In Platform Designer, click System > Show System With Platform Designer Interconnect.
  4. In the Memory-Mapped Interconnect tab, select the interconnect module that contains the critical path.
    You can determine the name of the module from the hierarchical node names in the timing report.
  5. Click Show Pipelinable Locations. Platform Designer display all possible pipeline locations in the interconnect. Right-click the possible pipeline location to insert or remove a pipeline stage.
  6. Locate the possible pipeline location that is closest to the mid-point of the critical path. The names of the blocks in the memory-mapped interconnect tab correspond to the module instance names in the timing report.
  7. Right-click the location where you want to insert a pipeline, and then click Insert Pipeline.
  8. Regenerate the Platform Designer system, recompile the design, and then rerun timing analysis.
  9. If necessary, repeat the manual pipelining process again until the design meets the timing requirements.

Manual pipelining has the following limitations:

  • If you make changes to the original system's connectivity after manually pipelining an interconnect, the inserted pipelines may become invalid. Platform Designer displays warning messages when you generate the system if invalid pipeline stages are detected. You can remove invalid pipeline stages with the Remove Stale Pipelines option in the Memory-Mapped Interconnect tab. Do not make changes to the system's connectivity after manual pipeline insertion.
  • Review manually-inserted pipelines when upgrading to newer versions of Platform Designer. Manually-inserted pipelines in one version of Platform Designer may not be valid in a future version.