Intel® Quartus® Prime Standard Edition User Guide: Platform Designer

ID 683364
Date 12/15/2018
Public
Document Table of Contents

2.6.2.3. Avalon® -MM Burst Master Example

Figure 63. Avalon Bursting Write MasterThis example shows the architecture of a bursting write master that receives data from a FIFO and writes the contents to memory. You can use a bursting master as a starting point for your own bursting components, such as custom DMAs, hardware accelerators, or off-chip communication interfaces.


The master performs word accesses and writes to sequential memory locations. When go is asserted, the start_address and transfer_length are registered. On the next clock cycle, the control logic asserts burst_begin, which synchronizes the internal control signals in addition to the master_address and master_burstcount presented to the interconnect. The timing of these two signals is important because during bursting write transfers byteenable and burstcount must be held constant for the entire burst.

To avoid inefficient writes, the master posts a burst when enough data is buffered in the FIFO. To maximize the burst efficiency, the master should stall only when a slave asserts waitrequest. In this example, the FIFO’s used signal tracks the number of words of data that are stored in the FIFO and determines when enough data has been buffered.

The address register increments after every word transfer, and the length register decrements after every word transfer. The address remains constant throughout the burst. Because a transfer is not guaranteed to complete on burst boundaries, additional logic is necessary to recognize the completion of short bursts and complete the transfer.