Intel® Quartus® Prime Standard Edition User Guide: Platform Designer

ID 683364
Date 12/15/2018
Public
Document Table of Contents

1.6.1. Platform Designer 64-Bit Addressing Support

Platform Designer interconnect supports up to 64-bit addressing for all Platform Designer interfaces and IP components, with a range of: 0x0000 0000 0000 0000 to 0xFFFF FFFF FFFF FFFF, inclusive.

The address parameters appear in the Base and End columns in the System View tab, on the Address Map tab, in the parameter editor, and in validation messages. Platform Designer displays as many digits as needed in order to display the top-most set bit, for example, 12 hex digits for a 48-bit address.

A Platform Designer system can have multiple 64-bit masters, with each master having its own address space. You can share slaves between masters, and masters can map slaves to different addresses. For example, one master can interact with slave 0 at base address 0000_0000_0000, and another master can see the same slave at base address c000_000_000.

Intel® Quartus® Prime debugging tools provide access to the state of an addressable system via the Avalon® -MM interconnect. These tools are also 64-bit compatible, and process within a 64-bit address space, including a JTAG to Avalon® master bridge.

Platform Designer supports auto base address assignment for Avalon® -MM components. In the Address Map tab, click Auto Assign Base Address.