Intel® Quartus® Prime Standard Edition User Guide: Platform Designer

ID 683364
Date 12/15/2018
Public
Document Table of Contents

7.1.1.1. add_interface

Description

Adds an interface to your module. An interface represents a collection of related signals that are managed together in the parent system. These signals are implemented in the IP component's HDL, or exported from an interface from a child instance. As the IP component author, you choose the name of the interface.

Availability

Discovery, Main Program, Elaboration, Composition

Usage

add_interface <name> <type> <direction> [<associated_clock>]

Returns

No returns value.

Arguments

name
A name you choose to identify an interface.
type
The type of interface.
direction
The interface direction.
associated_clock (optional)
(deprecated) For interfaces requiring associated clocks, use: set_interface_property <interface> associatedClock <clockInterface> For interfaces requiring associated resets, use: set_interface_property <interface> associatedReset <resetInterface>

Example

add_interface mm_slave avalon slave

add_interface my_export conduit end
set_interface_property my_export EXPORT_OF uart_0.external_connection

Notes

By default, interfaces are enabled. You can set the interface property ENABLED to false to disable an interface. If an interface is disabled, it is hidden and its ports are automatically terminated to their default values. Active high signals are terminated to 0. Active low signals are terminated to 1.

If the IP component is composed of child instances, the top-level interface is associated with a child instance's interface with set_interface_property interface EXPORT_OF child_instance.interface .

The following direction rules apply to Platform Designer-supported interfaces.

Interface Type Direction
avalon master, slave
axi master, slave
tristate_conduit master, slave
avalon_streaming source, sink
interrupt sender, receiver
conduit end
clock source, sink
reset source, sink
nios_custom_instruction slave