Intel® Quartus® Prime Standard Edition User Guide: Platform Designer

ID 683364
Date 12/15/2018
Public
Document Table of Contents

4.2.2.1. Error Response Slave Access Violation Service

When an access violation occurs, and the CSR port is enabled:
  1. The Error Response Slave generates an interrupt:
    • For a read access violation, the Error Response Slave sets the Read Access Violation Interrupt register bit in the Interrupt Status register.
    • For a write access violation, the Error Response Slave sets the Write Access Violation Interrupt register bit in the Interrupt Status register.
  2. The Error Response Slave transfers transaction information to the access violation log FIFO. The amount of information that the FIFO can handle is given by the Error Log Depth parameter.
    You define the Error Log Depth in the Parameter Editor, when you enable CSR Support.
  3. Software reads entries of the access violation log FIFO until the corresponding cycle log valid bit is cleared, and then exits the service routine.
    • The Read cycle log valid bit is in the Read Access Violation Log CSR Registers.
    • The Write cycle log valid bit is in the Write Access Violation Log CSR Registers.
  4. The Error Response Slave clears the interrupt bit when there are no access violations to report.
Some special cases are:
  • If any error occurs when the FIFO is full, the Error Response Slave sets the corresponding Access Violation Interrupt Overflow register bit (bits 2 and 3 of the Status Register for write and read access violations, respectively). Setting this bit means that not all error entries were written to the access violation log.
  • After Software reads an entry in the Access Violation log, the Error Response Slave can write a new entry to the log.
  • Software can specify the number of entries to read before determining that the access violation service is taking too long to complete, and exit the routine.