Intel® Quartus® Prime Standard Edition User Guide: Platform Designer

ID 683364
Date 12/15/2018
Public
Document Table of Contents

3.9.2.2. Cacheable (Modifiable)

Platform Designer interconnect acknowledges the cacheable (modifiable) attribute of AXI transactions.

It does not change the address, burst length, or burst size of non-modifiable transactions, with the following exceptions:

  • Platform Designer considers a wide transaction to a narrow slave as modifiable because the size requires reduction.
  • Platform Designer may consider AXI read and write transactions as modifiable when the destination is an Avalon® slave. The AXI transaction may be split into multiple Avalon® transactions if the slave is unable to accept the transaction. This may occur because of burst lengths, narrow sizes, or burst types.

Platform Designer ignores all other bits, for example, read allocate or write allocate because the interconnect does not perform caching. By default, Platform Designer considers Avalon® master transactions as non-bufferable and non-cacheable, with the allocate bits tied low.