Visible to Intel only — GUID: mwh1409959317999
Ixiasoft
Visible to Intel only — GUID: mwh1409959317999
Ixiasoft
4.1.7.1. AXI Timeout Bridge Stages
A timeout occurs when the internal timer in the bridge exceeds the specified number of cycles within which a burst must complete from start to end.
- When a timeout occurs, the AXI Timeout Bridge asserts an interrupt and reports the burst that caused the timeout to the Configuration and Status Register (CSR).
- The bridge then generates error responses back to the master on behalf of the unresponsive slave. This stage frees the master and certifies the unresponsive slave as dysfunctional.
- The AXI Timeout Bridge accepts subsequent write addresses, write data, and read addresses to the dysfunctional slave. The bridge does not accept outstanding write responses, and read data from the dysfunctional slave is not passed through to the master.
- The awvalid, wvalid, bready, arvalid, and rready ports are held low at the master interface of the bridge.
Write channel refers to the AXI write address, data and response channels. Similarly, read channel refers to the AXI read address and data channels. AXI write and read channels are independent of each other. However, when a timeout occurs on either channel, the bridge generates error responses on both channels.
Channel | Start | End |
---|---|---|
Write | When an address is issued. First cycle of awvalid, even if data of the same burst is issued before the address (first cycle of wvalid). | When the response is issued. First cycle of bvalid. |
Read | When an address is issued. First cycle of arvalid. | When the last data is issued. First cycle of rvalid and rlast. |
The AXI Timeout Bridge has four required interfaces: Master, Slave, Configuration and Status Register (CSR) ( AMBA* 3 AXI-Lite), and Interrupt. Platform Designer allows the AXI Timeout Bridge to connect to any AMBA* 3 AXI, AMBA* 3 AXI, or Avalon® master or slave interface. Avalon® masters must utilize the bridge’s interrupt output to detect a timeout.
The bridge slave interface accepts write addresses, write data, and read addresses, and then generates the SLVERR response at the write response and read data channels. Do not use buser, rdata and ruser at this stage of processing.
To resume normal operation, the dysfunctional slave must be reset and the bridge notified of the change in status via the CSR. Once the CSR notifies the bridge that the slave is ready, the bridge does not accept new commands until all outstanding bursts are responded to with an error response.
The CSR has a 4-bit address width and a 32-bit data width. The CSR reports status and address information when the bridge asserts an interrupt.
Address | Attribute | Name |
---|---|---|
0x0 | write-only | Slave is reset |
0x4 | read-only | Timed out operation |
0x8 through 0xF | read-only | Timed out address |