Intel® Quartus® Prime Standard Edition User Guide: Platform Designer

ID 683364
Date 12/15/2018
Public
Document Table of Contents

4.4.3.3.1. Test Pattern Generator Control and Status Registers

Table 99.  Test Pattern Generator Control and Status Register MapShows the offset for the test pattern generator control and status registers. Each register is 32-bits wide.
Offset Register Name
base + 0 status
base + 1 control
base + 2 fill
Table 100.  Test Pattern Generator Status Register Bits
Bits Name Access Description
[15:0] ID RO A constant value of 0x64.
[23:16] NUMCHANNELS RO The configured number of channels.
[30:24] NUMSYMBOLS RO The configured number of symbols per beat.
[31] SUPPORTPACKETS RO A value of 1 indicates data packet support.
Table 101.  Test Pattern Generator Control Register Bits
Bits Name Access Description
[0] ENABLE RW Setting this bit to 1 enables the test pattern generator core.
[7:1] Reserved
[16:8] THROTTLE RW

Specifies the throttle value which can be between 0–256, inclusively. The test pattern generator uses this value in conjunction with a pseudo-random number generator to throttle the data generation rate.

[17] SOFT RESET RW When this bit is set to 1, all internal counters and statistics are reset. Write 0 to this bit to exit reset.
[31:18] Reserved
Table 102.  Test Pattern Generator Fill Register Bits
Bits Name Access Description
[0] BUSY RO A value of 1 indicates that data transmission is in progress, or that there is at least one command in the command queue.
[6:1] Reserved
[15:7] FILL RO The number of commands currently in the command FIFO.
[31:16] Reserved