Intel® Quartus® Prime Standard Edition User Guide: Platform Designer

ID 683364
Date 12/15/2018
Public
Document Table of Contents

4.1.8.4. Using the Address Span Extender

This example shows when and how to use address span extender component in your Platform Designer design.

Figure 125. Block Diagram with Address Span Extender

In the above design, a 32-bit master shares 4 GB SDRAM with an external streaming interface. The master has the path to access streaming data from the SDRAM DDR memory. However, if you connect the whole 32-bit address bus of the master to the SDRAM DDR memory, you cannot connect the master to peripherals such as LED or UART. To avoid this situation, you can implement the address span extender between the master and DDR memory. The address span extender allows the master to access the SDRAM DDR memory and the peripherals at the same time.

To implement address span extender for the above example, you can divide the address window of the address span extender into two sub-windows of 512 MB each. The sub-window 0 is for the master program area. You can dynamically map the sub-window 1 to any area other than the program area.

You can change the offset of the address window by setting the base address of sub-window 1 to the control register of the address span extender. However, you must make sure that the sub-window address span masks the base address. You can choose any arbitrary base address. If you set the value 0xa000_0000 to the control register, Platform Designer maps the sub-window 1 to 0xa000_0000.

Table 93.  CSR Mapping Table
Address Data

0x8000_0000

0x0000_0000

0x8000_0008

0xa000_0000

Figure 126. Memory mapping for Address Span Extender

The table below indicates the Platform Designer parameter settings for this address span extender example.

Table 94.  Parameter Settings for the Address Span Extender Example
Parameter Value Description

Datapath Width

32 bits

The CPU has 32-bits data width and the SDRAM DDR memory has 512-bits data width. Since the transaction between the master and SDRAM DDR memory is minimal, set the datapath width to align with the upstream master.

Expanded Master Byte Address

32 bits

The address span extender has a 4 GB address span.

Slave Word Address Width

18 bits

There are two 512 MB sub-windows in reserve for the master. The number of bytes over the data word width in the Datapath Properties (4 bytes for this example) accounts for the slave address.

Burstcount Width

4 bits

The address span extender must handle up to 8 words burst in this example.

Number of sub-windows

2

Address window of the address span extender has two sub-windows of 512 MB each.

Enable Slave Control Port

true

The address span extender component must have control to change the base address of the sub-window.

Maximum Pending Reads

4

This number is the same as SDRAM DDR memory burst count.

Figure 127. Address Span Extender Parameter Editor
Note: You can view the address span extender connections in the System View tab. The windowed slave port and control port connect to the master. The expanded master port connects to the SDRAM DDR memory.