Intel® Quartus® Prime Standard Edition User Guide: Platform Designer

ID 683364
Date 12/15/2018
Public
Document Table of Contents

4.6.1. Delay Core Reset Signal

The Avalon® -ST Delay core has a reset signal that is synchronous to the clk signal. When the core asserts the reset signal, the output signals are held at 0. After the reset signal is deasserted, the output signals are held at 0 for N clock cycles. The delayed values of the input signals are then reflected at the output signals after N clock cycles.