Intel® Quartus® Prime Standard Edition User Guide: Platform Designer

ID 683364
Date 12/15/2018
Public
Document Table of Contents

1.13.1. Generation Dialog Box Options

Platform Designer system generation creates files for Intel® Quartus® Prime synthesis and supported third-party simulators. The Generation dialog box appears when you click Generate HDL, or when you attempt to close a system prior to generation.

You can specify the following system generation options in the Generation dialog box:

Table 14.   Generation Dialog Box Options
Option Description
Create HDL design files for synthesis Allows you to specify Verilog or VHDL file type generation for the system's top-level definition and child instances. Select None to skip generation of synthesis files.
Create timing and resource estimates for each IP in your system to be used with third-party synthesis tools Generates a non-functional Verilog Design File (.v) for use by supported third-party EDA synthesis tools. Estimates timing and resource usage for the IP component. The generated netlist file name is <ip_component_name>_syn.v.
Create Block Symbol File (.bsf) Generates a Block Symbol File (.bsf) for use in a larger system schematic Block Diagram File (.bdf).
Generate IP Core Documentation Generates the IP user guide documentation for the components in your system (when available).
Create simulation model Allows you to generate Verilog HDL or VHDL simulation model and simulation script files.
Note: ModelSim* - Intel® FPGA Edition supports native, mixed-language (VHDL/Verilog/SystemVerilog) simulation. Therefore, Intel simulation libraries may not be compatible with single language simulators. If you have a VHDL-only license, some versions of ModelSim® simulators may not support simulation for IPs written in Verilog. As a workaround, you can use ModelSim* - Intel® FPGA Edition, or purchase a mixed language simulation license from Mentor.
Path Specifies the output directory path.