Intel® Quartus® Prime Standard Edition User Guide: Platform Designer

ID 683364
Date 12/15/2018
Public
Document Table of Contents

4.1.2.2. Avalon® -MM Clock Crossing Bridge Parameters

Table 84.   Avalon® -MM Clock Crossing Bridge Parameters
Parameters Values Description
Data width 8, 16, 32, 64, 128, 256, 512, 1024 bits Determines the data width of the interfaces on the bridge, and affects the size of both FIFOs. For the highest bandwidth, set Data width to be as wide as the widest master that connects to the bridge.
Symbol width 1, 2, 4, 8, 16, 32, 64 (bits) Number of bits per symbol. For example, byte-oriented interfaces have 8-bit symbols.
Address width 1-32 bits The address bits needed to address the downstream slaves.
Use automatically-determined address width - The minimum bridge address width that is required to address the downstream slaves.
Maximum burst size 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024 bits Determines the maximum length of bursts that the bridge supports.
Command FIFO depth

2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384 bits

Command (master-to-slave) FIFO depth.
Respond FIFO depth

2, 4, 8,16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384 bits

Slave-to-master FIFO depth.
Master clock domain synchronizer depth 2, 3, 4, 5 bits The number of pipeline stages in the clock crossing logic in the issuing master to target slave direction. Increasing this value leads to a larger mean time between failures (MTBF). You can determine the MTBF for a design by running a timing analysis.
Slave clock domain synchronizer depth 2, 3, 4, 5 bits The number of pipeline stages in the clock crossing logic in the target slave to master direction. Increasing this value leads to a larger meantime between failures (MTBF). You can determine the MTBF for a design by running a timing analysis.