Intel® Quartus® Prime Standard Edition User Guide: Platform Designer

ID 683364
Date 12/15/2018
Public
Document Table of Contents

4.2.2.2. CSR Interrupt Status Registers

Table 96.  CSR Interrupt Status RegistersFor CSR register maps: Address = Memory Address Base + Offset.
Offset Bits Attribute Default Description
0x00 31:4 Reserved.
  3 RW1C 0

Read Access Violation Interrupt Overflow register

Asserted when a read access causes the Interconnect to return a DECERR response, and the buffer log depth is full. Indicates that there is a logging error lost due to an exceeded buffer log depth. Cleared by setting the bit to 1.

  2 RW1C 0

Write Access Violation Interrupt Overflow register

Asserted when a write access causes the Interconnect to return a DECERR response, and the buffer log depth is full. Indicates that there is a logging error lost due to an exceeded buffer log depth. Cleared by setting the bit to 1.

  1 RW1C 0

Read Access Violation Interrupt register

Asserted when a read access causes the Interconnect to return a DECERR response. Cleared by setting the bit to 1.

Note: Access violation are logged until the bit is cleared.
  0 RW1C 0

Write Access Violation Interrupt register

Asserted when a write access causes the Interconnect to return a DECERR response. Cleared by setting the bit to 1.

Note: Access violation are logged until the bit is cleared.