Intel® Quartus® Prime Standard Edition User Guide: Platform Designer

ID 683364
Date 12/15/2018
Public
Document Table of Contents

1.17. Creating a System with Platform Designer Revision History

The following revision history applies to this chapter:

Document Version Intel® Quartus® Prime Version Changes
2018.12.15 18.1.0
  • Moved command-line utility information into new "Platform Designer Command-Line Interface" chapter.
  • Revised headings and re-organized content into user task-based sections.
2018.09.24 18.1.0
  • Initial release in Intel Quartus Prime Standard Edition User Guide.
  • Removed duplicated topic: Manually Control Pipelining in the Platform Design Interconnect. The topic is now in the Platform Design Interconnect chapter.
  • Reorganized information about associating Intel Quartus Prime projects to Platform Designer systems.
  • Grouped information regarding definition and management of IP cores in Platform Designer under topic: IP Cores in Platform Designer, and updated contents.
  • In topic 64-Bit Addressing Support, added link to information about the auto base assignment feature.
2017.11.06 17.1.0
  • Changed instances of Qsys to Platform Designer (Standard)
2016.05.03 16.0.0
  • Qsys Command-Line Utilities updated with latest supported command-line options.
  • Added: Generate Header Files
2015.11.02 15.1.0
  • Added: Troubleshooting IP or Qsys System Upgrade.
  • Added: Generating Version-Agnostic IP and Qsys Simulation Scripts.
  • Changed instances of Quartus II to Quartus Prime.
2015.05.04 15.0.0
  • New figure: Avalon-MM Write Master Timing Waveforms in the Parameters Tab.
  • Added Enable ECC protection option, Specify Qsys Interconnect Requirements.
  • Added External Memory Interface Debug Toolkit note, Generate a Qsys System.
  • Modelsim-Altera now supports native mixed-language (VHDL/Verilog/SystemVerilog) simulation, Generating Files for Synthesis and Simulation.
December 2014 14.1.0
  • Create and Manage Hierarchical Qsys Systems.
  • Schematic tab.
  • View and Filter Clock and Reset Domains.
  • File > Recent Projects menu item.
  • Updated example: Hierarchical System Using Instance Parameters
August 2014 14.0a10.0
  • Added distinction between legacy and standard device generation.
  • Updated: Upgrading Outdated IP Components.
  • Updated: Generating a Qsys System.
  • Updated: Integrating a Qsys System with the Quartus II Software.
  • Added screen shot: Displaying Your Qsys System.
June 2014 14.0.0
  • Added tab descriptions: Details, Connections.
  • Added Managing IP Settings in the Quartus II Software.
  • Added Upgrading Outdated IP Components.
  • Added Support for Avalon-MM Non-Power of Two Data Widths.
November 2013 13.1.0
  • Added Integrating with the .qsys File.
  • Added Using the Hierarchy Tab.
  • Added Managing Interconnect Requirements.
  • Added Viewing Qsys Interconnect.
May 2013 13.0.0
  • Added AMBA APB support.
  • Added qsys-generate utility.
  • Added VHDL BFM ID support.
  • Added Creating Secure Systems (TrustZones) .
  • Added CMSIS Support for Qsys Systems With An HPS Component.
  • Added VHDL language support options.
November 2012 12.1.0
  • Added AMBA AXI4 support.
June 2012 12.0.0
  • Added AMBA AX3I support.
  • Added Preset Editor updates.
  • Added command-line utilities, and scripts.
November 2011 11.1.0
  • Added Synopsys VCS and VCS MX Simulation Shell Script.
  • Added Cadence Incisive Enterprise (NCSIM) Simulation Shell Script.
  • Added Using Instance Parameters and Example Hierarchical System Using Parameters.
May 2011 11.0.0
  • Added simulation support in Verilog HDL and VHDL.
  • Added testbench generation support.
  • Updated simulation and file generation sections.
December 2010 10.1.0 Initial release.