Intel® Quartus® Prime Standard Edition User Guide: Platform Designer

ID 683364
Date 12/15/2018
Public
Document Table of Contents

3.9.6.1. AXI and Avalon® Ordering

There is a potential read-after-write risk when Avalon® masters transact to AXI slaves.

According to the AMBA* Protocol Specifications, there is no ordering requirement between reads and writes. However, Avalon® has an implicit ordering model that requires transactions from a master to the same slave to be in order.

In response to this potential risk, Avalon® interfaces provide a compile-time option to enforce strict order. When turned on, the Avalon® interface waits for outstanding write responses before issuing reads.