Intel® Quartus® Prime Standard Edition User Guide: Platform Designer

ID 683364
Date 12/15/2018
Public
Document Table of Contents

4.1.3. Avalon® -MM Pipeline Bridge

The Avalon® -MM Pipeline Bridge inserts a register stage in the Avalon® -MM command and response paths. The bridge accepts commands on its slave port and propagates the commands to its master port. The pipeline bridge provides separate parameters to turn on pipelining for command and response signals.

The Maximum pending read transactions parameter is the maximum number of pending reads that the Avalon® -MM bridge can queue up. To determine the best value for this parameter, review this same option for the bridge's connected slaves and identify the highest value of the parameter, and then add the internal buffering requirements of the Avalon® -MM bridge. In general, the value is between 4 and 32. The limit for maximum queued transactions is 64.

You can use the Avalon® -MM bridge to export a single Avalon® -MM slave interface to control multiple Avalon® -MM slave devices. The pipelining feature is optional.

Figure 112.  Avalon® -MM Pipeline Bridge in a XAUI PHY Transceiver IP CoreIn this example, the bridge transfers commands received on its slave interface to its master port.

Because the slave interface is exported to the pins of the device, having a single slave port, rather than separate ports for each slave device, reduces the pin count of the FPGA.