Intel® Quartus® Prime Standard Edition User Guide: Platform Designer

ID 683364
Date 12/15/2018
Public
Document Table of Contents

4.4.1.1. Test Pattern Generator Command Interface

The command interface for the Test Pattern Generator is a 32-bit Avalon® -MM write slave that accepts data generation commands. It is connected to a 16-element deep FIFO, thus allowing a master peripheral to drive commands into the test pattern generator.

The command interface maps to the following registers: cmd_lo and cmd_hi. The command is pushed into the FIFO when the register cmd_lo (address 0) is addressed. When the FIFO is full, the command interface asserts the waitrequest signal. You can create errors by writing to the register cmd_hi (address 1). The errors are cleared when 0 is written to this register, or its respective fields.