Intel® Quartus® Prime Standard Edition User Guide: Platform Designer

ID 683364
Date 12/15/2018
Public
Document Table of Contents

3.1.6. Memory-Mapped Arbiter

The input to the Memory-Mapped Arbiter is the command packet for all masters requesting access to a specific slave. The arbiter outputs the channel number for the selected master. This channel number controls the output of a multiplexer that selects the slave device.
Figure 92. Arbitration LogicIn this example, four Avalon® ‑MM masters connect to four Avalon® ‑MM slaves. In each cycle, an arbiter positioned in front of each Avalon® ‑MM slave selects among the requesting Avalon® ‑MM masters.
Note:

If you specify a Limit interconnect pipeline stages toparameter greater than zero, the output of the Arbiter is registered. Registering this output reduces the amount of combinational logic between the master and the interconnect, increasing the fMAX of the system.

Note: You can use the Memory-Mapped Arbiter for both round-robin and fixed priority arbitration.