Intel® Quartus® Prime Standard Edition User Guide: Platform Designer

ID 683364
Date 12/15/2018
Public
Document Table of Contents

3.14.1. AXI Master Interface Signal Types

Table 68.  AXI Master Interface Signal Types
Name Direction Width
araddr output 1 - 64
arburst output 2
arcache output 4
arid output 1 - 18
arlen output 4
arlock output 2
arprot output 3
arready input 1
arsize output 3
aruser output 1 - 64
arvalid output 1
awaddr output 1 - 64
awburst output 2
awcache output 4
awid output 1 - 18
awlen output 4
awlock output 2
awprot output 3
awready input 1
awsize output 3
awuser output 1 - 64
awvalid output 1
bid input 1 - 18
bready output 1
bresp input 2
bvalid input 1
rdata input 8, 16, 32, 64, 128, 256, 512, 1024
rid input 1 - 18
rlast input 1
rready output 1
rresp input 2
rvalid input 1
wdata output 8, 16, 32, 64, 128, 256, 512, 1024
wid output 1 - 18
wlast output 1
wready input 1
wstrb output 1, 2, 4, 8, 16, 32, 64, 128
wvalid output 1