Intel® Quartus® Prime Standard Edition User Guide: Platform Designer

ID 683364
Date 12/15/2018
Public
Document Table of Contents

1.6.4.2. Wire-Level Expression Syntax

The wire-level expression derives from Verilog syntax. The following is an example and list of legal operators and elements that you can use for wire-level expressions.

Example Expressions:

foo1.port1[5:0] = foo2.port1[5:0]
foo3.port1[8:4] = foo5.port1[4:0] & 5’b10101
foo6.port1[0] = ‘b1
foo7.port1 = foo8.port1
foo9.port1[0] = ~foo10.port1[0] 
foo10.port1[3:0] = foo11.port2[1:0] + 4’b1100
foo12:port1[3:0] = {4{0}}
foo13.port1[7:0] = {foo14.port1[3:0], 4’b0011} 
Table 3.  Ports
Port Description
<instance_name>.<port_name> Whole port
<instance_name>.<port_name>[x] Wire x of port
<instance_name>.<port_name>[y:x] Wires x to y of port. Port ranges must be in decreasing order, for example a[1:0].
<constant base x values> For example: 1, ’b1, 4’hf, 4’o7, 32’d9
Table 4.  Operators (Bitwise)
Operator Description
~ Negation
& AND
| OR
~& NAND
~| NOR
^ XOR
~^ XNOR
Table 5.  Operators (Logical)
Operator Description
? Conditional
! Negation
&& AND
|| OR
Table 6.  Operators (Relational, Equality, and Shift)
Operator Description
> Greater Than
< Less Than
>= Greater Than or Equal To
<= Less Than or Equal To
== Equal To
!= Not Equal To
<< Shift Left
>> Shift Right
Table 7.  Operators (Mathematical)
Operator Description
+ Addition
- Subtraction
* Multiplication
/ Division
% Modulus
Table 8.  Operators (Other)
Operator Description
{integer {x}} Replication of x
{x, y, ...} Concatenation