DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 12/12/2022

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7.13.28. Wide Single-Channel Accumulators

This example design shows various ways to connect up an adder, sample delay (depth=1), and optional multiplexer to implement reset or load.

The output type of the adder is propagated from one of the inputs. You must select the correct input, otherwise the accumulator fails to schedule. You may add a Convert block to ensure the accumulator also maintains sufficient precision.

The wide single-channel accumulator consists of a two-input adder and sample-delay feedback with one cycle of latency. If you use a fixed-point input to this accumulator, you can make it arbitrarily wide provided the types of the inputs match with a data type prop duplicate block. The output type of the Add block can be with or without word growth. Alternatively, you can propagate the input type to the output of the adder.

The optional use of a two-to-one multiplexer allows the accumulator to load values according to a Boolean control signal. The inputs differ in precision, so the type with wider fractional part must be propagated to the output type of the adder, otherwise the accumulator fails to schedule. Converting both inputs to the same precision ensures that the single-channel accumulator can always be scheduled even at high fMAX targets.

If neither input has a fixed-point type that is suitable for the adder to output, use a Convert block to ensure that the precision of both inputs to the Add block are the same. Scheduling of this accumulator at high fMAX fails.

The model file is demo_wide_accumulators.mdl.

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