DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 12/12/2022

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Document Table of Contents Channelization for Four Channels with a Folding Factor of 3

Figure 13. Channelization for Four Channels with a Folding Factor of 3Combines four input channels into two wires (ChanCount = 4, ChanWireCount = 2, ChanCycleCount = 2). In Two wires are required to carry the four channels and the cycle count is two on each wire. DSP Builder distributes the channels evenly on each wire leaving the third time slot as do not care on each wire
Note: The generated Help page for the block shows the input and output data channel format that the FIR or CIC filter use after you have run a Simulink simulation.