DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 12/12/2022

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4.4. Verifying your DSP Builder Design with C++ Software Models

You can generate C++ software models for designs that support bit-accurate or bit-and-cycle-accurate simulation. Designs containing bus blocks do not support these two simulation modes. The C++ software models create a design as it functions on the hardware, as they are not purely algorithmic models. The models operate in the same way as the DSP Builder design operates on the FPGA hardware. For example, the models have the same latency as the design.