DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 12/12/2022

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15.4.53. Sequence

The Sequence block outputs a Boolean pulse of configurable duration and phase.

The input acts as an enable for this sequence. Usually, this block initializes with an array of Boolean pulses of length period. The first step_value entries are zero, and the remaining values are one.

A counter steps along this array, one entry at a time, and indexes the array. The output value is the contents of the array. The counter is initialized to initial_value. The counter wraps at step period, back to zero, to index the beginning of the array.

Table 244.  Parameters for the Sequence Block
Parameter Description
Output data type mode Determines how the block sets its output data type:
  • Inherit via internal rule: the number of integer and fractional bits is the maximum of the number of bits in the input data types.
  • Specify via dialog: you can set the output type of the block explicitly using additional fields that are available when this option is selected.This option reinterprets the output bit pattern from the LSB up according to the specified type.
  • Boolean: the output type is Boolean.
Output data type Specifies the output data type. For example, sfix(16), uint(8).
Output scaling value Specifies the output scaling value. For example, 2^-15.
Sequence setup A vector that specifies the counter in the format: [<initial_value> <step_value> <period>]

For example, [0 50 100]

Table 245.  Port Interface for the Sequence Block
Signal Direction Type Description Vector Data Support Complex Data Support
a Input Boolean Sequence enable Yes No
q Output Boolean Result Yes No