DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 12/12/2022

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7.7.8. Newton Root Finding Tutorial Step 3—Valid

This design example is part of the Newton-Raphson tutorial. It demonstrates how you avoid having the same answer multiple times on the output. It introduces a valid control signal, parallel to the datapath, to keep track of which pipeline slots the design empties. It uses equivalence groups in the minimum SampleDelay blocks.

The model file is demo_newton_valid.mdl.