DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 12/12/2022

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7.14.10. 4-Carrier, 2-Antenna High-Speed W-CDMA DUC at 368.64 MHz with Total Rate Change 32

This reference design uses IP and Interface blocks to build a high-speed 16-channel, 2-antenna, multiple-frequency modulation DUC for use in an IF modem design compatible with the W-CDMA standard.

The top-level testbench includes Control, Signals, and Run Quartus Prime blocks. A Spectrum Scope block computes and displays the periodogram of the outputs from the two antennas.

The DUCChip subsystem includes a Device block to specify the target FPGA device, and a DUC subsystem that contains InterpolatingFIR, InterpolatingCIC, NCO, ComplexMixer, and Scale blocks.

The FIR and CIC filters implement an interpolating filter chain that up converts the 16-channel input data from a frequency of 3.84 MSPS to a frequency of 122.88 MSPS (a total interpolation factor of 32). This design example uses dummy signals and carriers to achieve the desired rate up conversion, because of the unusual FPGA clock frequency and total rate change combination. The complex mixer and NCO modulate the four channel baseband input signal onto the IF region. The design example configures the NCO with four channels to provide four pairs of sine and cosine waves at frequencies of 12.5 MHz, 17.5 MHz, 22.5 MHz and 27.5 MHz, respectively. The NCO has the same sample rate (122.88 MSPS) as the final interpolated output sample rate from the last CIC filter in the interpolating filter chain.

The Sync subsystem shows how to manage two data streams that come together and synchronize. The data from the NCOs writes to a memory with the channel as an address. The data stream uses its channel signals to read out the NCO signals, which resynchronizes the data correctly.

The GenCarrier subsystem manipulates the NCO outputs to generate carrier signals that can align with the datapath signals.

The CarrierSum and SignalSelector subsystems sum up the right modulated signals to the designated antenna.

A system clock rate of 368.64 MHz, which is 96 times the input sample rate, drives the design on the FPGA, which the Device block defines inside the DUC subsystem. The higher clock rate can potentially allow resource re-use in other modules of a digital system implemented on an FPGA.

The model file is mcducmix96x32R.mdl.

Note: This reference design uses the Simulink Signal Processing Blockset.