DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 12/12/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

7.4.11. Interpolating CIC Filter

This design example implements an interpolating CIC filter.

The top-level testbench includes Control, Signals, Run ModelSim, and Run Quartus Prime blocks, plus ChanView block that deserialize the output buses. An Edit Params block allows easy access to the setup variables in the setup_demo_icic.m script.

The FilterSystem subsystem includes the Device and InterpolatingCIC blocks.

The model file is demo_icic.mdl.

Note: This design example uses the Simulink Signal Processing Blockset.