DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 12/12/2022

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4.6. Verifying Your DSP Builder Design in Hardware

Alternatively, verify the hardware with the system in the loop.


  1. Set up verification structures around the DUT using on-chip RAMs. If the design interfaces to off-chip RAM for reading and storing data, the design requires no additional verification structures.
    1. Add buffers to load with test vectors for DUT inputs and logic to drive DUT inputs with this data.
    2. Add buffers to store the DUT results.
      • Use a SharedMem block from the Interface library to implement buffers. DSP Builder automatically generates processor interface to these blocks that it requires to load and read the buffers from MATLAB (with MATLAB API).
      • Use Counter blocks from the Primitive library or custom logic to implement a connection between the test buffers and DUT inputs and outputs.
      • Consider using RegField, RegBit, and RegOut blocks from the Interface library to control the system and poll the results from MATLAB. DSP Builder automatically generates a processor interface for these blocks.
  2. Assemble the high-level system in Platform Designer.
  3. Use appropriate Platform Designer library blocks to add debugging interfaces and data storage.
    1. Add PLLs to generate clocks with the required frequency. You can use separate clocks for the processor interface clock and system clock of the DSP Builder design, if you generate the DSP Builder design with Use separate bus clock option.
    2. Add debug host (JTAG/USB). All memory-mapped read and write requests go through this IP core. Connect it to DSPBA processor interface (Avalon memory-mapped agent) and any other IP that needs to be accessed from host.
    3. Add the DSP Builder top-level design with the source and sink buffers.
    4. If you assemble a system with a DSP Builder design that connects to off-chip memory, add an appropriate block to the Platform Designer system and connect it to the DSP Builder block interfaces (Avalon memory-mapped host). Also, connect the debug host to off-chip RAM so the host can access it.
  4. Create a Intel Quartus Prime project.
  5. Add your high-level Platform Designer system into a top-level module and connect up all external ports.
  6. Provide port placement constraints.
    If you are using on-chip RAMs for testing and JTAG-based debugging interface, you mainly need to place clock and reset ports. If you use off-chip RAM for data storage, provide more complex port assignments. Other assignments may be required based on the specific design and external interfaces it uses.
  7. Provide timing constraints.
  8. Intel recommends you open the Simulink Simulation > > Model Configuration Parameters, select Diagnostics > Connectivity, and select Unconnected block input/output ports: error.
Compile the design and load it into the FPGA.