DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 12/12/2022

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Document Table of Contents Hardware Verification Design Example

DSP Builder design example for off chip source and sink buffers.
Figure 30. Top-Level SystemShows source and sink buffers and DUT.
Figure 31. Source Buffer AddressGen block triggers reads from SharedMem to drive DUT input. RegField initiates execution of the AddressGen block from host.
Figure 32. Sink Buffer
Figure 33.  Platform Designer System master_0 is the instance of JTAG debug master. syscon_api_sil_ex_0 is the instance of the top-level DSP Builder system, which contains test buffers.
Figure 34. MATLAB API