DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 12/12/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

7.13.17. Matrix Initialization of Vector Memories

Use this feature in DSP Builder designs that handle vector data and require individual components of each vector in the dual memory to be initialized uniquely.

The design example file is demo_dualmem_matrix_init.mdl.

You can initialize both the dual memory and LUT Primitive library blocks with matrix data.

The number of rows in the 2D matrix that you provide for initialization determines the addressable size of the dual memory. The number of columns must match the width of the vector data. So the nth column specifies the contents of the nth dual memory. Within each of these columns the ith row specifies the contents at the (i –- 1)th address (the first row is address zero, second row address 1, and so on).

The exception for this row and column interpretation of the initialization matrix is for 1D data, where the initialization matrix consists of either a single column or single row. In this case, the interpretation is flexible and maps the vector (row or column) into the contents of each dual memory. In the previous behavior all dual memories have identical initial contents.

The demo_dualmem_matrix_init design example uses complex values in both the initialization and the data that it later writes to the dual memory. You set up the contents matrix in the model's set-up script, which runs on model initialization.