DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 12/12/2022

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5.3. Simulating the Fibonacci Design in Simulink


  1. Click Simulation > Run.
  2. Double-click on the Scope block and click Autoscale in the scope to display the simulation results .
    Figure 39. Fibonacci Sequence in the Simulink Scope
    Note: You can verify that the fib output continues to increment according to the Fibonacci sequence by simulating for longer time periods.
    The sequence on the fib output starts at 0, and increments to 1 when q_v and q_c are both high at time 21.0. It then follows the expected Fibonacci sequence incrementing through 0, 1, 1, 2, 3, 5, 8, 13 and 21 to 34 at time 30.0.