DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 12/12/2022

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7.14.15. Crest Factor Reduction

This reference design implements crest factor reduction, based on the peak cancelling algorithm.

For further information refer to the web page.

You can change the simulation length by clicking on the Simulink Length block.

The model file is demo_cfr.mdl.