DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 12/12/2022

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Document Table of Contents Channelization for Two Channels with a Folding Factor of 3

If the number of channels is greater than the period, multiple wires are required. Each IP block in your design is internally vectorized to build multiple blocks in parallel.
Figure 12. Channelization for Two Channels with a Folding Factor of 3Combines two input channels into a single output wire (ChanCount = 2, ChanWireCount = 1, ChanCycleCount = 2). Three available time slots exist in the output channel and every third time slot has a “don’t care” value when the valid signal is low. The value of the channel signal while the valid signal is low does not matter.