DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 12/12/2022

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5.4. Modifying the DSP Builder Fibonacci Design to Generate Vector Signals

Simulate the design.


  1. In the Scope Design Outputs scope zoom in on the y axis to see the short Fibonacci cycle.
    Figure 40. Fibonacci Scope Design Outputs
  2. Copy the real input block, add a Simulink mux and connect to the Convert block.
  3. Edit the timing of the real1 block, for example [0 1 1 1 zeros(1,50)].