DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 12/12/2022

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7.13.1. 8×8 Inverse Discrete Cosine Transform

This design example uses the Chen-Wang algorithm to implement a fully pipelined 8×8 inverse discrete cosine transform (IDCT).

Separate subsystems perform the row transformation (Row), corner turner (CornerTurn), and column transformation (Col) functions. The design example synthesizes each separate subsystem separately. The Row and Col subsystems have additional levels of hierarchy for the different stages. The SynthesisInfo block is at the row or column level, so the design example flattens these subsystems before synthesis.

The CornerTurn turn block makes extensive use of Simulink Goto/From blocks to reduce the wiring complexity. The top-level testbench includes Control and Signals blocks. The IDCTChip subsystem includes the Device block and a lower level IDCT subsystem. The IDCT subsystem includes lower level subsystems that it describes with the ChannelIn, ChannelOut, Const, BitCombine, Shift, Mult, Add, Sub, BitExtract, SampleDelay, OR Gate, Not, Sequence, and SynthesisInfo blocks.

The model file is demo_idct8x8.mdl.