DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 12/12/2022

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4.2. Verifying your DSP Builder Advanced Blockset Design in Simulink and MATLAB

Use this early verification to focus on the functionality of your algorithm, then iterate the design implementation if needed. DSP Builder generates synthesizable VHDL for the design at the start of every Simulink simulation. DSP Builder generates an automatic testbench for the whole design and each subsystem. You can use these testbenches to play data that the Simulink simulation captures through the generated VHDL in ModelSim and confirm the results are identical.