DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 12/12/2022

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Document Table of Contents

8.2. Troubleshooting DSP Builder Designs

You might see errors when you build, test, update, simulate, or verify your DSP Builder design.


  1. Check your design construction:
    • Follow the recommendations for structuring and managing your model.
    • Follow the Simulink setup guidelines.
    • Follow the design rules
    • Follow the rules for Primitive and IP library blocks and specific blocks like SampleDelays blocks
  2. Check for common Simulink errors including algebraic loops and unresolved data types.
  3. Ensure your DSP Builder does not use Primitive library blocks in unsupported modes – either outside of primitive subsystems or in loops without sufficient start to end of loop timing offset.
  4. Read DSP Builder error messages to see the root cause.
  5. Click DSP Builder > Design Checker, to check your design for common mistakes.
  6. Select individual steps and click Check.
    The output only matches the hardware when valid is high.
    If your design uses FIFO buffers within multiple feedback loops, while the data throughput and frequency of invalid cycles is the same, their distribution over a frame of data might vary (because of the final distribution of delays around the loop). If you find a mismatch, step past errors.