DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 12/12/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

15.6.17. Zero-Latency Latch (latch_0L)

The DSP Builder latch_0 block enable signal has an immediate effect on the output. While the enable is high, the data passes straight through. When the enable goes low, the latch_0 block outputs and holds the data input from the previous cycle.

The e signal is a ufix(1) enable signal. When e is high, the latch_0 block feeds data from input d through to output q. When e is low, the latch_0 block holds the last output.

A switch in e is effective immediately.