DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 12/12/2022

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Document Table of Contents

7.12.2. 16-Channel DUC

This design example shows how to build a 16-channel DUC as found in modern radio systems using Interface, IP, and Primitive blocks.

This design example shows an interpolating filter chain with interpolating CIC and FIR filters that up convert eight complex channels (16 real channels). The total interpolation rate is 50. DSP Builder integrates several Primitive subsystems into the datapath. This design example shows how you can integrate IP blocks with Primitive subsystems:

  • The programmable Gain subsystem, at the start of the datapath, shows how you can use processor-visible register blocks to control a datapath element.
  • The Sync subsystem is a Primitive subsystem that shows how to manage two data streams coming together and synchronizing. The design writes the data from the NCOs to a memory with the channel as an address. The data stream uses its channel signals to read out the NCO signals, which resynchronizes the data correctly. Alternatively, you can simply delay the NCO value by the correct number of cycles to ensure that the NCO and channel data arrive at the Mixer on the same cycle.

Extensive use is made of Simulink multiplexer and demultiplexer blocks to manage vector signals.

The top-level testbench includes Control, Signals, Run ModelSim, and Run Quartus Prime blocks, plus a ChanView block that deserializes the output bus. An Edit Params block allows easy access to the setup variables in the setup_demo_duc.m script.

The DUCChip subsystem includes a Device block and a lower level DUC16 subsystem.

The DUC16 subsystem includes InterpolatingFIR, InterpolatingCIC, ComplexMixer, NCO, and Scale blocks.

It also includes lower level Gain, Sync, and CarrierSum subsystems which make use of other Interface and Primitive blocks including AddSLoad, And, BitExtract, ChannelIn, ChannelOut, CompareEquality, Const, SampleDelay, DualMem, Mult, Mux, Not, Or, RegBit, RegField blocks, and SynthesisInfo blocks.

The model file is demo_duc.mdl.

Note: This design example uses the Simulink Signal Processing Blockset.