DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 12/12/2022

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10.1.6. Ready Signal

The ready signal is an output that goes high to indicate when you can input data into your design. It provides flow control that allows you to reduce jitter in your design. The ready signal output is high when the internal architecture is idle.
Figure 95. Ready Signal Timing